IEEE802_1AS: IEEE 802.1AS Hardware Protocol Stack

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Industrial, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The IEEE802_1AS is a complete IEEE 802.1AS hardware stack that enables the simple and rapid development of time-aware nodes for AVB/TSN networks such as automotive Ethernet. It operates fully autonomously and provides timing and synchronization according to IEEE 802.1AS for full-duplex, point-to-point Ethernet links. The core is designed to operate next to an Ethernet Media Access Control unit (eMAC) and attached to that eMAC’s data-interface towards the host system. It automatically synchronizes its internal real-time clock (RTC) to that of the grandmaster by inserting and extracting IEEE 802.1AS frames in and from the Ethernet traffic. The core fully offloads the host processor from any IEEE 802.1AS related processing, and at the same time enables the development of time-aware applications: it provides timestamps, periodic event triggers, and alarms to the host system, using host processor Interrupt lines or dedicated-low latency interface signals.

Features

  • Complete IEEE 802.1AS hardware stack enabling rapid development of time-aware AVB/TSN nodes.
  • Automatically synchronizes internal Real-Time Clock to Grandmaster’s time
  • Returns timestamps to the system using absolute time and supports programmable alarm to assert host interrupt at specified absolute time
  • Provides periodic event triggers, with events periods being independent from absolute time changes
  • Includes a QSYS project using a NIOS-based system, and an Altera Eclipse project for a sample software application

Device Utilization and Performance

The IEEE802_1AS core can be mapped to any Intel FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The core occupies approximately 4,000 ALMs. Please contact CAST to discuss resource utilization and performance for your application and target device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
QSYS project
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim, Questa, NCSIM
Hardware validated Y. Altera Board Name Cyclone V GX Starter Kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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