This JPEG-D-S core is a high-performance JPEG decoder supporting the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It is suitable for decompressing JPEG images and the video payload of Motion-JPEG container formats.. The core decodes one color sample per clock cycle, and is able to process Full-HD 1080p video in most FPGA devices. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.
The JPEG-X-S core can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The core occupies approximately 4,000 ALMs, 5 DSPs and 32Kbits of memory, and can process 1080p60 on Arria 10 or Stratix V devices, or 720p60 in Max 10 devices. Please contact CAST to discuss resource utilization and performance for your application and target device.
IP Quality Metrics
|Year IP was first released||2016|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Any additional customer deliverables provided with IP||Software Model|
|Parameterization GUI allowing end user to configure IP||N|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||N|
|Driver OS support||Drivers are not required|
|IP-XACT Metadata included||N|
|Simulators supported||Modelsim, Questa, NCSIM|
|Hardware validated||Y. Altera Board Name StartixV GX and Arria V development kits|
|Industry standard compliance testing performed||N|
|If No, is it planned?||N|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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