JPEG-E-S: Baseline JPEG Encoder

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V


This IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with very low processing latency. The JPEG-E-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats. The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it synthesizes to about 3,500 ALMs. The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access.


    Device Utilization and Performance

    The JPEG-E-S core can be mapped to any Altera Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The size of the core depends on its configuration. Under its default configuration it occupies approximately 3,500 ALMs, 4 DSPs and 50Kbits of memory, and can process 1080p60 in 4:2:2 format on Arria 10 device. Under the same configuration the core can process 1080p30 in 4:2:2 format on Max 10 devices. Please contact CAST to discuss resource utilization and performance for your application and target device.

    Getting Started

    Contact CAST at to arrange for a core evaluation

    IP Quality Metrics

    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Bit Accurate Software Model
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNot required
    User InterfaceAXI
    IP-XACT Metadata includedN
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated Y. Altera Board Name ArriaV-GX Devkit
    Industry standard compliance testing performed
    If No, is it planned?N
    IP has undergone interoperability testing
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.