JPEG-EX-F: Ultra-Fast, 4K/8K, Baseline and Extended JPEG Encoder

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

This IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less power than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-EX-F Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bits per color samples and up to four color components, in all widely-used color subsampling formats. Depending on its configuration, the encoder processes from 2 to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame video. The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access.

Features

    Device Utilization and Performance

    The JPEG-EX-F core can be mapped to any Altera Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The size of the core depends on its configuration. For example a core configured to process 2 pixels per cycle (JPEG-EXF/2) occupies approximately 6,000 ALMs, 8 DSPs and 80Kbits of memory, and can process UHD/4k at 30fps on Arria 10 device. Under the same configuration the core can process 1080p60 in Max 10 devices. Faster processing rates are feasible in most Altera FPGAs. Please contact CAST to discuss resource utilization and performance for your application and target device.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Bit-Accurate Software Model
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNot required
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated Y. Altera Board Name ArriaV GX devkit
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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