L8051XC1: Legacy-Configurable 8051-Compatible Microcontroller IP Core

Block Diagram

Solution Type: IP Core

End Market: Consumer, Industrial, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The L8051XC1 megafunction implements an MCS 51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems. The megafunction can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from Intel, Phillips/NXP, Siemens/Infineon, Maxim/Dallas, Texas instruments and others. Several pre-configured versions are offered; custom variations are also available.

Features

    Device Utilization and Performance

    L8051XC1 designs have been evaluated in a variety of technologies. The megafunction optimized for speed, while assuming that all megafunction I/Os are routed off-chip, and configured with 2 times, 1 serial & 4 parallel ports used 2,684 LEs and reaches 75 MHz.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceOther: Native
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, Questa, NC-SIM
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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