MD5: MD5 Processor Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a variety of applications. It computes a 120-bit message digest for messages of up to (2**64 – 1) bits. The MD5 algorithm is an improved version of the MD4, created by Professor Ronald L. Rivest of MIT, and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 128-bit (4 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message.

Features

  • RFC 1321 compliant
  • Maximum message length is 2**64 - 1
  • Throughput: 7.9 Mbits/MHz
  • Size: From 730 ALMs
  • Deliverables include test benches, C model and test vector generator

Device Utilization and Performance

The core can be mapped to any Altera Family and optimized to suit the particular project's requirements. The MD5 core synthesizes to 730 ALMs. On Arria10 device, the core can run at least 100MHz providing a throughput of 787Mbps.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2006
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Bit Accurate Model
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: generic uP
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated N. Altera Board Name Altera Cyclone V SOC Board
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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