MTS-E: MPEG Transport Stream Multiplexing & Encapsulation Engine

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Consumer, Industrial, Military, Test & Measurement

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The MTS-E megafunction multiplexes and encapsulates audio, video and metadata streams in a single MPEG Transport Stream (TS), and optionally encapsulates the TS packets in Real-Time Transport Protocol (RTP) packets. Under its default configuration, the MTS-E multiplexing and encapsulation engine supports two input stream channels, e.g., one Audio and one Video. Configurations with more than two input stream channels can be made available upon request. The output transport stream can be forwarded for local storage or transmitted over an Internet Protocol (IP) or other network. Streaming over IP networks often imposes further encapsulation of the transport stream in RTP, UDP, and IP packets. The MTS-E megafunction can be programmed to perform RTP encapsulation, while the companion UDPIP megafunction from CAST supports UDP/IP encapsulation.

Features

    Device Utilization and Performance

    MTS-E reference designs have been evaluated in a variety of technologies. The megafunction configured with one input stream channel, no RTP, no TS packet grouping an no Program ES info support uses 678 ALMs and 65,536 RAM bits in an Arria V device.

    Getting Started

    Contact CAST at info@cast-inc.com to evaluate the core

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNone
    Implementation
    User InterfaceAXI; Other: AXI4-Lite, AXI4-Streaming
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, Questa, NC-SIM
    Hardware validated Y. Altera Board Name DK-DEV-4SGX230N & DK-START-5AGXB3N
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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