PCI-M64: 64-bit, 66 MHz PCI Master/Target Interface Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: Interface Protocols: PCI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The main PCI-M64 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development. The PCI-M64 Interface supports 64-bit address/data bus and operates up to 66 MHz (PCI clock frequency). It is fully compliant with the PCI Local Bus Specification, Revision 2.3. The PCI-M64 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required. The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are: a) Configuration Read, Configuration Write b) Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL) and c) I/O Read, I/O Write.

Features

  • 64-bit DMA Controller supporting independent write and read operations available
  • Zero wait states burst mode, type 0 configuration space and parity generation and parity error detection
  • PCI specification 2.3 compliant Master/Target, 66 MHz optional, 64-bit datapath
  • Support all interrupt pins, all Base Address Registers, and backend initiated target retry, disconnect and abort

Device Utilization and Performance

The core synthesizes to about 600 LEs

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2008
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated Y. Altera Board Name Cyclone V
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.