SCR: Smart Card Reader Controller

Block Diagram

Solution Type: IP Core

End Market: Consumer, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore, OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The SCR core implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR supports the ISO/IEC 7816-3:1997(E) and EMV2000 4.0 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions. The SCR consists of the core smart card reader logic with a wrapper for the desired system interface. (AMBA APB and Wishbone interfaces are available; support for other bus interfaces is optional.)

Features

    Device Utilization and Performance

    The core synthesizes to about 750 LEs.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2005
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, Questa, NC-SIM
    Hardware validated N. Altera Board Name DE0 Nano
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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