SHA-1: Secure Hash Algorithm Cryptoprocessor Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The SHA-1 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (2**64 – 1) bits. Developed for easy reuse, the SHA-1 is available optimized for several technologies with competitive utilization and performance characteristics. Support for the AMBA bus interface is available as an option.

Features

    Device Utilization and Performance

    The core can be mapped to any Altera Family and optimized to suit the particular project's requirements. The SHA-1 core synthesizes to 620 ALMs. On Arria10 device, the core can run at least 100MHz providing a throughput of 632Mbps.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2002
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Bit Accurate Model
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceOther: generic uP; AMBA
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, Questa, NC-SIM
    Hardware validated N. Altera Board Name Altera Cyclone V SOC Board
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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