SHA-3: SHA-3 Secure Hash Function Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The SHA-3 IP core is a high-throughput, area-efficient hardware implementation of the SHA-3/Kaccak cryptographic hashing functions, compliant to NISTS's FIPS 180-4 and FIPS 202 standards. The core can implement any one of the four cryptographic SHA-3 hash functions provisioned by the standards: SHA3-224, SHA3-256, SHA3-384, and SHA3-512. Its throughput can optionally be optimized by using input message buffering, which allows it to receive new input while still processing the previous message. Also, the number of hashing rounds per clock is configurable at synthesis time, allowing users to constrain performance to save silicon resources when desired. The SHA-3 IP core can ensure data integrity and/or user authentication in a range of applications including IPsec and TLS/SSL protocol engines, encrypted data storage, secure processing systems, e-commerce, and financial transaction systems.

Features

    Device Utilization and Performance

    The core can be mapped to any Altera Family and optimized to suit the particular project's requirements. The SHA-3 core synthesizes to about 3,000 ALMs when no buffers are implemented and from 4.3k ALMs (for SHA3-512) to 6.1k ALMs (for SHA3-224) when two input buffers are implanted. On an Arria10 device, the core can run at 150MHz providing a throughput of 7.2Gbps for SHA3-224, 6.8Gbps for SHA3-256, 5.2 Gbps for SHA3-384, and 3.6 Gbps for SHA3-512.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNot required
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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