UDPIP-40G: 40G UDP/IP Hardware Protocol Stack

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Stratix Series: Stratix V

Overview

The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 40Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo Request and Reply Messages of the ICMP widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN. The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers mapped on an SoC bus.

Features

    Device Utilization and Performance

    The silicon resources requirements depend on the core configuration. A quad channel core synthesizes to approximately 7,500 ALMs and requires 400k bits of memory, while a single channel core synthesizes to approximately 97,000 ALMs and requires 800k bits of memory. To deliver a 40Gbps under the worst case scenario, the core needs to be clocked at 312.5MHz, however running the core at 200MHz should suffice to deliver 40Gbps in realistic UDP/IP traffic scenarios.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Wrapper integrating core with Intel FPGA 40G Ethernet MAC
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNot required
    Implementation
    User InterfaceOther: AXI-Stream, or Avalon-ST
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated Y. Altera Board Name StratixIV GX DevKit
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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