ZipAccel-C: GZIP/ZLIB/Deflate Data Compression Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Military, Wireless

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. The megafunction receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the megafunction encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the megafunction?s input. The megafunction's flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as a few tens of clock cycles.

Features

  • Processor-free, standalone operation; optional ECC memories
  • Fine-tune Throughput, Compression Efficiency, and Latency to match application requirements
  • Configurable: search engine & Huffman encoder architecture; history search window size; deflate block size; etc.
  • LZ77 with conf. block & search window size; Static and Dynamic Huffman; Optional Stored Deflate Blocks; Dynamic Mode Selection
  • Deflate Standards: Deflate (RFC-1951) - ZLIB (RFC-1950) - GZIP (RFC-1952)

Device Utilization and Performance

ZipAccel-C reference designs have been evaluated in a variety of technologies. ZipAccel-C performance can scale by instantiating more search engines and/or Huffman decoders. Furthermore, other design options such as the search area window affect the silicon resources utilization. When configured with 1 Search Engine, 1 Dynamic Huffman Encoder, 4 KB History Window with a clock constraint of 200 MHz it uses 10,768 ALMs and 281,294 RAM bits in a Stratix V device.

Getting Started

Contact CAST at info@cast-inc.com to evaluate the core

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Bit Accurate Model
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNone
Implementation
User InterfaceAXI; Other: Streaming capable i/f
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated N. Altera Board Name Various
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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