ZipAccel-D: GUNZIP/ZLIB/Inflate Data Decompression Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Military, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards. The megafunction features fast processing, with low latency and high throughput. On average the megafunction outputs two bytes of decompressed data per clock cycle, providing over 5Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the megafunction multiple times to achieve throughput rates exceeding 100Gbps.The latency for blocks coded with Static Huffman is in the order of few tens of clock cycles, and blocks coded with Dynamic Huffman get processed in less than 1500 cycles.

Features

    Device Utilization and Performance

    ZipAccel-D reference designs have been evaluated in a variety of technologies. ZipAccel-D performance can scale by instantiating more Huffman decoders and by using multiple megafunction instances. The core configured with Static Huffman only uses 2,281 ALMs and 20,160 RAM bits in an Arria 10 device.

    Getting Started

    Contact CAST at info@cast-inc.com to evaluate the core

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNone
    Implementation
    User InterfaceAXI; Other: Streaming-capable i/f
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, Questa, NC-SIM
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.