ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards. The megafunction features fast processing, with low latency and high throughput. On average the megafunction outputs two bytes of decompressed data per clock cycle, providing over 5Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the megafunction multiple times to achieve throughput rates exceeding 100Gbps.The latency for blocks coded with Static Huffman is in the order of few tens of clock cycles, and blocks coded with Dynamic Huffman get processed in less than 1500 cycles.
ZipAccel-D reference designs have been evaluated in a variety of technologies. ZipAccel-D performance can scale by instantiating more Huffman decoders and by using multiple megafunction instances. The core configured with Static Huffman only uses 2,281 ALMs and 20,160 RAM bits in an Arria 10 device.
IP Quality Metrics
|Year IP was first released||2011|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Parameterization GUI allowing end user to configure IP||N|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||N|
|Driver OS support||None|
|User Interface||AXI; Other: Streaming-capable i/f|
|IP-XACT Metadata included||N|
|Simulators supported||ModelSim, Questa, NC-SIM|
|Hardware validated||N. Altera Board Name NULL|
|Industry standard compliance testing performed||N|
|If No, is it planned?||N|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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