DVB-C / J.83abc Modulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Modulation and Demodulation

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The CMS0024 Cable Modulator is fully compliant with the European, US, and Japanese downlink cable standards DVB-C and J.83abc, providing all the necessary functions between transport stream input and QAM output. The core can be configured to support from one to four FDM channels with additional (independent) channels accommodated by the instantiation of multiple single or multi-channel cores per FPGA. For more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/cable_mod.htm

Features

  • Compliant with DVB-C (EN 300 429) and ITU J.83 Annexes A, B and C including DOCSIS 1.1/2.0
  • 16, 32, 64, 128 and 256 QAM
  • Arbitrary symbol rate up to a quarter of the applied master clock frequency
  • Scalable architecture supports from one to four channels per core and multiple cores per FPGA
  • Short (16kb) and normal (64Kb) frames

Device Utilization and Performance

Approximate size estimates for typical CMS0024 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations. Alternative FPGA targets may also be available, please contact Commsonic for further information.

Getting Started

Please contact Commsonic at info@commsonic.com for further information.

IP Quality Metrics

Basic
Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportC-code API
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone-III 3c25 Starter Kit.
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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