DVB-S / DVB-DSNG Modulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Test & Measurement, Wireless

Evaluation Method: OpenCore Plus

Technology: DSP: Modulation and Demodulation

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The CMS0010 DVB-S modulator / DSNG modulator is an integrated modulator and Reed-Solomon encoder core designed specifically to address the requirements of the ETSI DVB-S forward-link satellite Standard (EN300421). The core can be extended to include the trellis coding as required by the ETSI DVB-DSNG forward-link satellite Standard (EN301210). For further or more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/SDvbSModulator.htm.

Features

  • Compliant with DVB-S (EN 300 421) and DVB-DSNG (EM 301 210)
  • Variable sample-rate interpolation provides ultra flexible clocking strategy.
  • QPSK, 8PSK, 16-QAM.
  • Optional DVB-CID modulation support.

Device Utilization and Performance

Approximate size estimates for typical CMS0010 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations. Alternative FPGA targets may also be available, please contact Commsonic for further information.

Getting Started

Please contact Commsonic at info@commsonic.com for further information.

IP Quality Metrics

Basic
Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportC-code API
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone-III 3c25 Starter Kit.
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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