ISDB-T Modulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Test & Measurement, Wireless

Evaluation Method: OpenCore Plus

Technology: DSP: Modulation and Demodulation

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The ISDB-T modulator / ISDB-TB modulator core enables rapid development of audio and visual systems using commodity free-to-air set-top-box products. The specification is fully supported by the ISDB-T modulator for 2K, 4K and 8K COFDM modes as well as hierarchical transport streams. The ISDB-T modulator / ISDB-TB modulator targets SDRAM for minimum cost but also supports synchronous SRAM or internal FPGA RAM, allowing flexible implementation on a range of platforms. For more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/TIsdbTModulator.htm

Features

  • Variable channel bandwidth support using a single clock reference.
  • 1-segment or 13-segment operation
  • Hierarchical transmission - configurable for up to 3 layers.
  • Supports SDRAM or Synchronous SRAM
  • Extension cores for BTS and SFN synchronisation

Device Utilization and Performance

Approximate size estimates for typical CMS0045 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations. Alternative FPGA targets may also be available, please contact Commsonic for further information.

Getting Started

Please contact Commsonic at info@commsonic.com for further information.

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportC-code API
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone-V Starter Kit.
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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