DVB-RCS2 Turbo Encoder/Decoder

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites. It uses a new 16-state double- binary turbo decoder that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes. New modulation schemes (8-PSK and 16-QAM) help to increase spectral efficiency even further. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.


  • -compliant with ETSI 301 545-2 V1.1.1 (2012-01) DVB-RCS2
  • -support for all DVB-RCS2 payload block sizes (14 to 599 bytes) and code rates (1/3 to 7/8)
  • -support for all modulation schemes (QPSK, 8-PSK, 16-QAM)

Device Utilization and Performance

-payload throughput of up to 148 Mbit/s at 5 iterations and 92 Mbit/s at 8 iterations (200 MHz) -BER 10-⁸ with code rate 3/4 at Es/No = 4 dB (QPSK, 298 payload bites) Es/No = 8.9 dB (8 PSK, 400 payload bites) Es/No =10.9 dB (16-QAM, 539 payload bites)

Getting Started

Please contact Creonic Sales Team!

IP Quality Metrics

Year IP was first released2013
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
User InterfaceOther: proprietary
IP-XACT Metadata includedN
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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