DVB-S2X Wideband Decoder IP

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Creonic DVB-S2X Wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs.

Features

    Device Utilization and Performance

    symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs

    Getting Started

    Contact sales@creonic.com to request more information on our IP Cores

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported17.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    No
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportn/a
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, RivieraPRO
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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