GEO-Mobile Radio LDPC Decoder

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

GEO-Mobile Radio (GMR) is an ETSI standard for satel- lite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time. The same burst modes and LDPC codes are also in GMR Re- lease 3 (GMR-3G). The Creonic GMR LDPC decoder IP core is a field-proven solution.

Features

  • -compliant with GMR Release 2, ETSI TS 101 376-5-3 V2.3.1 (2008-07) (GMPRS-1 05.003)
  • -compliant with GMR Release 3, ETSI TS 101 376-5-3 V3.1.1 (2009-07) (GMR-3G 45.003)
  • -support for return and forward link
  • -support for short PNB2 (5,3) bursts and long PNB2 (5,12) bursts
  • -support for all PNB2 modulation schemes (Pi/4-QPSK, 16-APSK, 32-APSK)

Device Utilization and Performance

-support for all PNB2 shortening, repeating, and puncturing schemes -support for all PNB2 LDPC codes (approximate channel coding rates 1/2, 2/3, 4/5, 9/10)

Getting Started

Please contact the Creonic Sales Team!

IP Quality Metrics

Basic
Year IP was first released2013
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
no
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceOther: proprietary
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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