CXC-1 Configurable Cross Converter

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix V


The CXC-1 is a parameterized integration of the VPC-1 Deinterlacer and VSC-1 Scaler IP cores along with all circuitry necessary to interface to a DRAM controller. The CXC-1 greatly simplifies using the VPC-1 and VSC-1 in a wide range of applications. All build-time parameters supported by the VPC-1 and VSC-1 are available at the top level of the CXC-1. Additional build-time parameters are provided to include or exclude certain processing blocks. This allows, for example, the CXC-1 to be configured as a full up/down/cross converter or as a deinterlacer only or a scaler only.


    Device Utilization and Performance

    16.5K ALMs, 885K bits, 45 DSPs (Cyclone V) Fmax = 150 MHz

    Getting Started

    Evaluation can be performed using pre-built bitstreams for standard Altera dev kits or a time-limited trial of the actual IP

    IP Quality Metrics

    Year IP was first released2014
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Reference design targeted to standard Altera FPGA dev kit
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportC/C++ support functions
    User InterfaceAXI; Avalon-MM; Other: Generic bus
    IP-XACT Metadata includedN
    Simulators supportedQuartus II Simulator, ModelSim
    Hardware validated Y. Altera Board Name Cyclone V GT FPGA Development Board
    Industry standard compliance testing performed
    If yes, which test(s)?HQV 2.0 Benchmark
    If yes, on which Altera device(s)?Cyclone V GT
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  N

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