VPC-1 Video Processor and Deinterlacer with Line-Doubled Output

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

The VPC-1 is a high quality motion adaptive deinterlacer and video processor with line-doubled output. Additional functions include motion adaptive noise reduction, low angle directional interpolation and film cadence detection (supports multiple cadences including 3:2, 2:2 and others). When combined with Crucial IP’s VSC-1 scaler core, the VPC-1 can be used to provide complete up/down/cross conversion. Years of experience in developing video processing algorithms have contributed to the outstanding performance of the VPC-1 amongst motion adaptive class solutions. The full feature set, robust performance and extremely efficient implementation make the VPC-1 ideal for both consumer electronic and broadcast applications.

Features

    Device Utilization and Performance

    9K ALMs, 346K bits, 9 DSPs (Cyclone V) Fmax = 150 MHz

    Getting Started

    Evaluation can be performed using pre-built bitstreams for standard Altera dev kits or a time-limited trial of the actual IP

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Reference design targeted to standard Altera FPGA dev kit
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportC/C++ support functions
    Implementation
    User InterfaceAXI; Avalon-MM; Other: Generic bus
    IP-XACT Metadata includedN
    Verification
    Simulators supportedQuartus II Simulator, ModelSim
    Hardware validated Y. Altera Board Name Cyclone V GT FPGA Development Board
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?HQV 2.0 Benchmark
    If yes, on which Altera device(s)?Cyclone V GT
    If Yes, date performed
    01/26/2016
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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