Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Industrial, Medical, Test & Measurement

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Arria V, Arria 10 SoC, Arria V SoC


AHCI PCIe SSD IP core (APS-IP) enables FPGA system to directly connect AHCI SSD without CPU support. Ultimate high speed storage application is now in your hands! APS-IP operating with Avalon-MM Hard IP for PCIe from Intel is ideal to access AHCI PCIe SSD without CPU and external memory such as DDR3 requirement. It is recommended to use in the application which require high capacity storage at very high-speed performance. Small size system can be also designed by M.2 storage which uses PCIe protocol standard. The IP core license includes the reference design for Intel FPGA boards. It is useful to shorten your development time. More information from here http://www.dgway.com/APS-IP_A_E.html


    Device Utilization and Performance

    Arria10 SX (10AS066N3F40E2SGE2) Fmax=250MHz, Logic utilization=628ALMs, Registers=923 / Arria V GX (5AGXFB3H4F35C4) / Arria V ST (5ASTFD5K3F40I3 ) : Fmax=125MHz, Logic utilization=593ALMs, Registers=790

    Getting Started

    1st Step: Download free evaluation sof file from DesignGateway official website (http://www.dgway.com/APS-IP_A_E.html) / 2nd Step: Adapter board is provided from DesignGateway / 3rd Step: Evaluate the IP core performance / 4th Step: Purchasing IP core /

    IP Quality Metrics

    Year IP was first released2016
    Latest version of Quartus supported16.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Reference Design
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportN/A
    User InterfaceOther: Customized
    IP-XACT Metadata includedN
    Simulators supportedModelsim Altera Edition
    Hardware validated Y. Altera Board Name Arria10 SX, Arria V GX, Arria V ST
    Industry standard compliance testing performed
    If No, is it planned?N
    IP has undergone interoperability testing
    Interoperability reports available  N

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