IPLock IPcore Protection System

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: Source Code

Technology: Basic Functions: Simulation, Debug and Verification

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

IP Lock is an FPGA logic security system which uses very reliable AES encryption technology. IP properties in the FPGA are protected from illegal copy by including IP Lock in the FPGA and connecting it with encryption controller chip.

Features

  • Strong security by AES encryption
  • Change & encrypt authentication data at about 200msec cycle, Stop user logic when removing the chip
  • Generate true random authentication data by natural random number generator
  • Connecting I/O with FPGA are only 2 pins
  • No need to input clock to IP Lock logic

Device Utilization and Performance

N/A

Getting Started

Step1: Prepare SOIC-8 pattern for security chip on your board >> Step2: When you need FPGA logic protection, purchase IPLock product >> Step3: Compile your FPGA logic with IPLock core >> Step4: Put IPLock security chip on FPGA board >> Step5: Complete IP core protection!

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
SOIC-8 encryption chip, software
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportWindows
Implementation
User InterfaceOther: 2.5-3.3V IO
IP-XACT Metadata includedN
Verification
Simulators supportedN/A
Hardware validated Y. Altera Board Name Cyclone III
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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