SATA AHCI IP core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: Source Code

Technology: Interface Protocols: Serial

Arria Series: Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V SoC

Overview

SATA AHCI IP core operating with SATA IP Core is suitable for the system which has the processor running on OS and needs to have SATA device to be the system storage. By using AHCI driver to access AHCI IP, the system can access SATA device with full features and high speed performance. ARM on Cyclone V/Arria V/Arria 10 SoC platform can be used to be the processor for AHCI IP, so the IP can be applied for embedded storage system, RAID application, high-speed and large capacity data acquisition systems. For more information, visit http://www.dgway.com/SATA-IP_A_E.html

Features

    Device Utilization and Performance

    [Implementation Statistics] Cyclone V SX (5CSXFC6D6F31C6) Fmax=100MHz, ALMs=636, Block Memory bit=666,112 Arria V ST (5ASTFD5K3F40I3) Fmax=150MHz, ALMs=629, Block Memory bit=666,112

    Getting Started

    1st Step: Download free evaluation sof file from DesignGateway official website. 2nd Step: Adapter board is provided from DesignGateway. 3rd Step: Evaluate the IP core performance. 4th Step: Purchasing. For more information, visit http://www.dgway.com/SATA-IP_A_E.html

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported16.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Reference Design
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceOther: Customized
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim Altera Edition
    Hardware validated Y. Altera Board Name Cyclone V SX SoC board /Arria V ST SoC board/Arria 10 SX SoC board
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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