UDP10G/1G-IP core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

UDP10G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time. DesignGateway provide demo file for Intel® FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing. http://www.dgway.com/UDP10G-IP_A_E.html

Features

  • All hardware logic to achive CPU-less system
  • Support IPv4 protocol
  • Simple data interface by standard FIFO interface and Simple control interface by standard register interface
  • Provide free evaluation sof file for FPGA Development Kits
  • Rerference design is included in IP core product

Device Utilization and Performance

Arria10 SX (10AS066N3F40E2SGE2) Fmax=156.25MHz, ALMs=1,327, Block Memory bit=1,179,648

Getting Started

1st Step: Download free evaluation sof file from DesignGateway official website. 2nd Step: Evaluate the IP core performance. 3rd Step: Purchasing IP core. For more information, visit http://www.dgway.com/UDP10G-IP_A_E.html

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference Design
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Customized
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim - Intel® FPGA Edition
Hardware validated Y. Altera Board Name Arria10 SX
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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