USB3.0 Host IP core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Test & Measurement

Evaluation Method: Source Code

Technology: Interface Protocols: Serial

Arria Series: Arria V

Cyclone Series: Cyclone IV, Cyclone V

Stratix Series: Stratix IV

Overview

USB3.0 (Host) IP Core is ideal for use in a USB3.0 supported device system which require high bandwidth up to 5.0Gbps. This IP Core will process almost all USB3.0 protocols by hardware. It achieves processing by low-end CPU. This IPcore provide link layer, protocol layer. Physical layer interfaces to PHY chip by TI. DesignGateway provide 1-hour limited sof file for Intel FPGA development kits. You can evaluate the performance before purchasing the IP core. More information from here http://www.dgway.com/USB3-IP_A_E.html

Features

    Device Utilization and Performance

    [Implementation Statistics] ArriaV GX (5AGXFB3H4F35C4) Fmax=142MHz, ALMs=5,816, Block Memory bit=135,168

    Getting Started

    1st Step: Download free evaluation sof file from DesignGateway official website. 2nd Step: Adapter board is provided from DesignGateway. 3rd Step: Evaluate the IP core performance. 4th Step: Purchasing IP core.

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Reference Design
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceOther: Customized
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim Altera Edition
    Hardware validated Y. Altera Board Name Cyclone IV GX, Cyclone V E, Arria V GX Development Kit
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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