D16550 - Configurable UART with FIFO

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

he D16550 is a soft Core of Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C550A. It allows serial transmission in two modes - UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both, receive and transmit directions. The D16550 performs serial-to-parallel conversion on data characters, received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters, received from the CPU. The CPU can read a complete status of the UART at any time, during the functional operation. Reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt).

Features

    Device Utilization and Performance

    Provided in the product datasheet

    Getting Started

    For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

    IP Quality Metrics

    Basic
    Year IP was first released2003
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportTBD
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim
    Hardware validated Y. Altera Board Name DE1, DE2
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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