D8254 - Programmable Interval Timer

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The D8254 is a programmable interval timer/counter, binary compatible with the 82C54 industry standard. Since DCD's core value is innovation, this unique IP Core solves one of the most common problems in any micro-computer system: the generation of accurate time delays under software control. The D8254 can be used as: - Real time clock - Even counter - Digital one-shot - Programmable rate generator - Square wave generator - Binary rate multiplier - Complex waveform generator - Complex motor controller - Interrupt on terminal count The D8254 includes fully automated testbench with complete set of tests which allows an easy package validation at each stage of SoC design flow. Our proprietary core is a technology independent design that can be implemented in a variety of process technologies.

Features

    Device Utilization and Performance

    Provided in product datasheet.

    Getting Started

    For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

    IP Quality Metrics

    Basic
    Year IP was first released2006
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportTBD
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim
    Hardware validated Y. Altera Board Name DE1, DE2
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  Y

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