D85C30 - UART Core with SDLC Function

Block Diagram

Solution Type: IP Core

End Market: Automotive, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The D85C30 - (Serial Communication Controller) is a dual channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device, designed for use with 8 and 16-bit microprocessors. It functions as serial-to-parallel, parallel-to-serial converter/controller and can be software-configured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated internal functions, including on-chip baud rate generators. The D85C30 handles asynchronous formats, synchronous byte-oriented protocols, such as IBM Bisync, and synchronous bit-oriented protocols, like HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (telecommunication, LAN, etc.). The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes.

Features

    Device Utilization and Performance

    Provided in the product datasheet.

    Getting Started

    For additional information, contact DCD at: Digital Core Design Wroclawska 94 41-902 Bytom Poland Tel. +48 32 282 82 66 Fax +48 32 282 74 37 E-mail: aleads@dcd.pl WWW: http://www.dcd.com.pl

    IP Quality Metrics

    Basic
    Year IP was first released2013
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportNA
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim
    Hardware validated Y. Altera Board Name DE1, DE2
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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