DBLCD32 - LCD/TFT Display Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The DCD’s DBLCD32 core is a fully configurable, universal LCD/TFT display controller. It supports a wide range of resolution and enables both, horizontal and vertical synchronization parameters setup. The display’s pixel clock can be generated by an internal pixel clock divider based on the bus clock, or delivered to the core by a dedicated pin. Additionally there is a possibility of using an externally generated pixel clock. Polarization of the generated pixel clock, as well as synchronization signals, is configurable. The DBLCD32 has a DMA capable master interface, which can be used to access a framebuffer placed directly in a system memory. Embedded DMA controller has configurable FIFO to store pixels data, which increases system throughput and performance. Transmission on the master interface is burst oriented and there is a possibility of defining the burst size limit. Data fetched by the DMA interface can be translated to 24-bits RGB signals, depending on the selected color mode.

Features

  • 24-bit RGB interface; Configurable display resolution; Configurable horizontal sync length and blanking
  • Configurable vertical sync length and blanking; Configurable RGB signals polarization; Configurable pixel clock polarization
  • Internal pixel clock divider; Different pixel clock modes; DMA capable interface; Configurable DMA FIFO; Configurable burst size limit
  • AHB bus interface(32-bit); 24-bit True Color mode support; 16-bit (5-6-5) High Color mode support; 8-bit Indexed Color mode support
  • 32-bit True Color mode support (one byte ignored); Pixel palette RAM; Page flipping support; Programmable interrupts; Big and little - endian support

Device Utilization and Performance

Provided in the product datasheet.

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Basic
Year IP was first released2010
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.