DCAN Configurable CAN Bus Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The DCAN is a standalone controller for the Controller Area Network (CAN), which is commonly used in automotive and industrial applications. What's most important, the DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). The Core has a simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO, enable a back-to-back message reception with a minimum CPU load. The DCAN is described at RTL level, allowing target use in FPGA technologies.

Features

  • Conforms to Bosch CAN 2.0B Active; 8/16/32-bit CPU slave interface with little or big endianess; Simple interface allows easy connection to CPU
  • Data rate up to 1 Mbps; Hardware message filtering (dual/single filter); 64 byte receive FIFO; One transmit buffer
  • Overload frame is generated on FIFO overflow; Normal & Listen Only Mode; Single Shot transmission
  • Ability to abort transmission; Readable error counters; Readable error counters
  • Available system interface wrappers: AMBA - APB Bus, Altera Avalon Bus, Xilinx OPB Bus

Device Utilization and Performance

Provided in the product datasheet

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Basic
Year IP was first released2001
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  Y

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