DLCD - LCD/TFT Display Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The DLCD is a display controller with 24-bit RGB output and synchronization. It may be used for displaying data, both on LCD and CRT displays. Pixel data has an 8-bit resolution and a 24-bit RGB output is generated using external LUT with defined color palette. Our "multimedial" Core is controlled by the CPU, which enables usage of external data memory to display data. All parameters are configurable through the CPU register interface. The core was designed to be used with DCD's DP80xxx series of MCU. The display controller is perfect for MCU based applications, where static graphic data is displayed using a LCD/TFT matrix or a CRT monitor. Our unique core is a technology independent design, that can be implemented in a variety of process technologies.

Features

  • Maximum resolution 1024 x 1024 pixels; 24-bit RGB output, 8-bit pixel with external LUT for color palette
  • Configurable screen parameters; Configurable memory data bus width; Wait states for memory access
  • Pixel clock divider; Display data copying without CPU access; Display data accessible for CPU as external data memory
  • Fully synthesizable; Static synchronous design and no internal tri-states

Device Utilization and Performance

Provided in the product datasheet.

Getting Started

For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: aleads@dcd.pl Website: http://www.digitalcoredesign.com

IP Quality Metrics

Basic
Year IP was first released2010
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
TBD
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportTBD
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name DE1, DE2
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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