Arria 10 System on Module "SoM"

Board Image

Block Diagram

Board Category: Development Kit

Components & Interface: Expansion: FMC, SPF Cage; Industry Standard: Ethernet, PCIE Edge, RS232, USB Device

End Market: Automotive, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Technology: DSP, Embedded Design, General Purpose, Interface Protocols

Board Feature: General User IO: LED

Arria Series: Arria 10 SoC: Arria 10 SX

Overview

The Arria 10 SoM was developed with an emphasis on embedded and automotive vision applications. Using Intels Arria 10 SoC devices in the 29x29 mm package, the module off ers a multitude of interfaces in a small 8 cm by 6,5 cm form factor. 32 versatile LVDS lanes are brought out to the module connectors, allowing a variety of customer specific high speed differential data IO with e.g. image sensors, displays, ADC or DACs. Each lane can individually be used as 2 independent 1.8V GPIOs as well to be able to e.g. hook up single ended control & status signals or other generic IO functions. All 12 RX/TX Gigabit transceivers can be used to implement high bandwidth video standards such as 12G SDI or DisplayPort. This requires a careful clocking strategy to minimize jitter for sensitive applications such as SDI. The four transceiver reference clock pins are partly connected to programmable clock generators on the module itself, the others are sourced from the base board to implement interfaces like PCIe Gen3 where the reference clock comes from the system or to allow for video genlocking. ƒƒ8x6,5 cm Module with two mezzanine connectors to a customer base board ƒƒIntel Arria 10 SoC FPGA with 160 to 480 KLEs and Cortex A9 Dual Core CPU ƒƒPower management on the module guarantees proper power-up and -down sequence, only 12V to be supplied by baseboard ƒƒTwo separate DDR4 memory interfaces ƒƒCPU Memory System –– 2GByte –– 32 Bit parallel Data Bus –– 8 Bit ECC supported for safety critical applications –– Up to 2.4Gbit/s per pin for a total bandwidth of 77Gbit/s ƒƒFPGA Memory System –– 4GByte –– 64 Bit parallel Data Bus –– Up to 2.4Gbit/s per pin for a total bandwidth of 153Gbit/s ƒƒAll 12 Transceivers at 12 GBit/s and above: –– Supports interfaces such as PCIe Gen3 x8, 10/40 GBit/s Ethernet, DisplayPort and 12G SDI –– Dedicated clocking on the module to provide lowest jitter for sensitive applications such as SD ƒƒUp to 32 LVDS lanes to the baseboard: –– each either RX or TX ––

Order Information

Ordering Code
Pricing
Buy
DCT10A-DEVKIT$1980Buy Now

Development Kit Hardware Contents

  • Arria 10 SoM with 480KLE
  • BaseBoard with power supply

Development Kit Software Contents

  • Linux Golden Reference Design
  • Example Implementations for Displayport, Ethernet, PCIe
  • OpenCL BSP HPS Host (on request)
  • OpenCL BSP x86 Host (on request)

Support Document

File Name
Description
Version
doc-us-dsnbk-179-3407332406363-dct-arria10-soc-som-folder-v3.pdfArria 10 SoM Overview3

Board Quality Metrics

Basic
Latest version of Quartus supported 16.1
Required Collateral Available
User Guide N
Board Schematics N
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

10
Parts per Million (PPM)
10
Board Policy
Return Material Authorization (RMA) Policy RMA number can be obtained at DCT
Compliance
RoHS Compliant Y
CE Compliant Y. Yes it is
Conflict Mineral Policy Compliant
N
Test Plan Summary

Example implementation of interfaces with top level as test an implementation guidance

Additional Compliance
ISO 9000 & 9001

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