Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


The SD/MMC SPI core with Altera Avalon bus interface allows the designer to easily connect Qsys systems to standard MMC and SD card flash-based memory devices. The MMC and SD cards are universal, low-cost data storage and communication media widely used in consumer products such as digital cameras and cellular phones. The SD/MMC SPI core is fully compliant with Qsys and integrates easily into any Qsys system.For the Nios II processor, El Camino provides low-level driver routines for the SD/MMC SPI core. The drivers provide universal access routines for MMC and SD memory devices, eliminating the need for additional low-level code to read or write raw data from or to the SD/MMC cards.


  • Optional Stand-Alone FAT12/16/32 file system support
  • More than 2400 kByte/s read and 2400 kByte/s write performance
  • Low-level drivers included and automatically integrated into NIOS HAL
  • Hardware assisted CRC calculation
  • Supports MultiMediaCard (MMC) and Secure Digital Card (SD, SDHC, SDXC) in SPI mode

Device Utilization and Performance

Depending on the target device family the IP core requires approximately 320 Logic Elements and supports system clocks around 180 MHz.

Getting Started

Contact El Camino to receive a free evaluation version of the core. This comes with a Qsys based example design that can easily be adapted to any standard prototyping kit or custom hardware platform. Furthermore we provide two software examples, one for low level FLASH like access as well as one for high level FAT12/16/32 file I/O.

IP Quality Metrics

Year IP was first released2005
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportNios HAL
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name e.g. Nios Embedded Evaluation Kit (NEEK)
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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