Display Controller IP Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: HDMI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Display Controller IP Core enables the easy addition of a display to existing or future FPGA designs, allowing the system designer to focus on the main application instead of dealing with display control issues. In addition, there is no need for an external display controller device that would consume precious PCB space and unnecessarily extend the project’s BOM. With its modular design and strong scalability, the Display Controller IP Core perfectly fits the system requirements without wasting any FPGA resources. These unique features will also simplify the reuse of the Display Controller IP Core in future projects. Selecting our Display Controller IP Core for the display control needs of present or future projects will significantly reduce time to market as well as the overall system cost.

Features

  • Support for parallel, LVDS and HDMI/DVI displays without external display controller device
  • Support for unlimited video pages
  • Built-in PWM generator for display brightness control
  • Optional 2D accelerator unit (draw/copy rectangles, supports transparent color)
  • Supported color modes: 16-bit true color (5/6/5) and 24-bit true color

Device Utilization and Performance

Cyclone V, 1024 Pixel Read Buffer, without 2D Accelerator, LVDS interface: 600 LUT, 750 REG, 4 BRAM (10k) Cyclone V, 1024 Pixel Read Buffer, with 2D Accelerator, LVDS interface: 1600 LUT, 1700 REG, 9 BRAM (10k)

Getting Started

Enclustra offers a free evaluation license with a reference design including a NIOS II to get started.

IP Quality Metrics

Basic
Year IP was first released2009
Latest version of Quartus supported15.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim PE
Hardware validated Y. Altera Board Name Enclustra Mercury SA1 & Mercury+ PE1
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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