UDP/IP Ethernet IP Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


Enclustra's UDP/IP Ethernet IP core easily enables FPGA-based subsystems to communicate with other subsystems via Ethernet, using the UDP protocol. The IP core is highly configurable and optimally implemented for the use in current Altera FPGAs and SoCs. It provides a simple to use interface to the user logic, and supports the common media independent interfaces MII, RMII, GMII and RGMII. With its 8-bit wide transmit and receive interfaces running at 125 MHz, the IP core is able to operate at full 1 Gbps wire speed. 100 Mbts and 10 Mbts operation is also supported.


  • Multiple UDP ports with dedicated receive and transmit interfaces for each port
  • Optional receive data buffers
  • Raw Ethernet port for non-UDP communication
  • Header pass-through mode
  • MII, RMII, GMII and RGMII media independent interfaces (full-duplex only)

Device Utilization and Performance

Cyclone IV, 1 UDP Interface, 2 receive buffer, 2000 byte payload: 3700 Logic Cells, 2700 Registers, 2200 LUT, 11 BRAM (M9k)

Getting Started

Enclustra offers a free evaluation license with a reference design and an evaluation kit to get started.

IP Quality Metrics

Year IP was first released2012
Latest version of Quartus supported15.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportDriver independent
User InterfaceOther: Stream / FIFO
IP-XACT Metadata includedN
Simulators supportedModelSim PE
Hardware validated Y. Altera Board Name Enclustra Mercury CA1, Mercury+ PE1
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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