Universal Drive Controller IP Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Industrial, Medical, Military

Evaluation Method: Source Code

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The Enclustra Universal Drive Controller IP Core enables the easy addition of drive control capabilities to existing or future FPGA designs. It supports DC, BLDC, 2- and 3-phase stepper motors. The Universal Drive Controller is available as Qsys component, meaning no HDL knowledge is required. A software API is provided with the IP core, allowing configuration of the Universal Drive Controller without having to know the exact layout of the register bank and the meaning of each field within every register. The completely autonomous error handling reduces the complexity for the user application further. A Separate PWM clock domain for high-resolution PWM is available. In a typical configuration, the Universal Drive Controller IP core is capable of executing around 1,000,000 device calculations per second independently of the device type (including FOC for BLDC motors). For example, this means that 4 BLDC motors with current control rates of up to 250kHz can be controlled simultaneously.

Features

    Device Utilization and Performance

    Clock frequency > 64 MHz Controller update rate (@64 MHz, 1 axis): Up to 1 MHz Device utilization strongly depends on the configuration of the IP-Core and the number of axes to support. Numbers for standard settings are given below (Cyclone V): 1 DC motor: ~4.5k ALM ~9 M10K ~2 DSP Blocks 1 BLDC motor: ~5k ALM ~11 M10K ~3 DSP Blocks

    Getting Started

    Enclustra offers a free evaluation license with a reference design running on a Cyclone V SoC and an evaluation kit to get started.

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported15.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportBare Metal
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim PE
    Hardware validated Y. Altera Board Name Enclustra Mercury SA1, Mercury+ PE1 & FMC-DR2
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.