32-Bit PCI Bus Master/Target Interface

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The 32-bit PCI master/target interface megafunction is a flexible interface between a bus master device, such as a direct-memory access (DMA) controller or video coprocessor, and the PCI bus. The megafunction supports high bandwidth data transfer up to 133 Mbytes per second. All PCI configuration registers are included in the megafunction, and configuration requests are processed locally by the megafunction. This megafunction also includes PCI target capability, which is useful for transferring data as a target and for setting up the control register of a bus mastering device. The megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format.

Features

    Device Utilization and Performance

    1193 LE

    Getting Started

    For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

    IP Quality Metrics

    Basic
    Year IP was first released2000
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportAll PCI compatible
    Implementation
    User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
    IP-XACT Metadata includedN
    Verification
    Simulators supportedVerilog/VHDL
    Hardware validated N. Altera Board Name Arrow SocKit
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?PCI Compliance
    If yes, on which Altera device(s)?Flex10K
    If Yes, date performed
    01/01/1997
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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