AHB to SDRAM Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


The AHB bus SDRAM controller provides high speed SDRAM access for the system. It features one AHB port for user to access SDRAM. It is also available in multipe port configuration for memory sharing. All the access port can be AHB or a mixture of other bus interface. A generic user interface can be provided for optimal system core logic or DMA access. The SDRAM controller contains built-in arbitration unit in the case of multiple port setup to allow both the AHB CPU and other system core logic to share SDRAM access. Sophisticated priority scheme allows data sharing to be customized to application requirements.


  • SDRAM controller interfaces directly with advanced high-performance bus (AHB) and user interface
  • Built-in arbitration between two access ports
  • Dual write buffer for simultaneous write posting and SDRAM access
  • Second access port allows memory sharing with user logic devices

Device Utilization and Performance

2646 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

IP Quality Metrics

Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportOS independent
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.