PCI-to-ISA Bridge

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Interface Protocols: PCI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The PCI-to-ISA bridge functions as a PCI target on the PCI bus. PCI transactions addressed to this target are forwarded to the ISA bus. If it is a read transfer, the core waits for all read data from the ISA slave and returns the data to the PCI bus. If it is a write transfer, the core posts the write data to its internal write buffer, terminates the PCI bus, and then writes the data to the ISA slave. With a typical PCI bus running at 33 MHz, this core operates the ISA bus at one-fourth the frequency of the PCI bus. The ISA bus operates at 8.33 MHz. The PCI-to-ISA bridge core supports 8-bit and 16-bit ISA bus devices, while the PCI bus is 32-bits wide. The core is capable of taking one PCI transfer and converting it into four or two transfers on the ISA bus. This megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements.

Features

    Device Utilization and Performance

    592 LE

    Getting Started

    For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

    IP Quality Metrics

    Basic
    Year IP was first released2000
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportAll PCI compatible
    Implementation
    User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
    IP-XACT Metadata includedN
    Verification
    Simulators supportedVerilog/VHDL
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?PCI Compliance
    If yes, on which Altera device(s)?Flex10K
    If Yes, date performed
    01/01/1997
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.