SD / SDIO / MMC Slave Controller (EP560)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The EP560 SD Slave Controller IP core provides the simplest way to design a Secure Digital (SD) or MultiMedia Card (MMC) device. It serves as a bridge between the SD bus and user's application logic inside the card. It contains many flexible design features that allows it to be easily integrated to any card applications. It supports SD memory, SDIO, SDHC, MMC and combo card functions.

Features

    Device Utilization and Performance

    3200 LE

    Getting Started

    For additional information, you can contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

    IP Quality Metrics

    Basic
    Year IP was first released2004
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportOS independent
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedVerilog/VHDL
    Hardware validated Y. Altera Board Name Custom build board
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?SD Specification
    If yes, on which Altera device(s)?Cyclone
    If Yes, date performed
    01/01/2004
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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