SD/SDIO 2.0 MMC Host Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


The EP550 SD/MMC host controller connects the host CPU to the system’s SD card socket to allow it to access SD/MMC cards. It supports SD2.0, SDHC, SDIO, SD Combo and MMC cards. The SD host controller core is compliant to the SD 2.0 host specification for 1 and 4-bit data transfer. This IP core offers a wide choice of CPU interface including AHB, AXI, Avalon, PLB and generic bus. To access SD card, the host CPU simply access the control registers inside the core. The core handles all the SD card protocol automatically including data shifting, timing and CRC. The core has built-in DMA controller so that data can be automatically transferred between system memory and the SD card without CPU intervention. The EP550 is recognized by any operating systems that supports the SD bus. No driver development is needed. Eureka also provides free source code to users who develop their own software.


  • Host controller for SD and SDIO 2.0 with option to support eMMC for 1, 4 and 8 bit data transfer
  • Choice of AHB, AXI, APB, Avalon, PLB, Wishbone and generic user interface
  • Supports SDMA operation for autonomous data transfer
  • Implement SD host controller standard register set and supports all standard SD/MMC bus drivers including Windows and Linux
  • Hardware handling of CRC error detection and interrupt generation

Device Utilization and Performance

2200 LE, 4 RAM blocks, 100 MHz

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: WWW:

IP Quality Metrics

Year IP was first released2004
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportOS independent
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
If yes, which test(s)?SD Specification
If yes, on which Altera device(s)?Cyclone
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.