SD/SDIO 3.0 Slave Controller (EP563)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The EP563 SD 3.0 Slave Controller IP core provides the simplest way to design a Secure Digital (SD) or MultiMedia Card (MMC) device. It serves as a bridge between the SD bus and user's application logic inside the card. It contains many flexible design features that allows it to be easily integrated to any card applications. It supports SD memory, SDIO, SDHC, MMC and combo card functions.

Features

  • Compatible with SD 3.0. Supports SD, SPI, SD Combo card, and optional 8-bit MMC bus protocol
  • USH-I Ultra High Speed up to 104Mbyte/sec and DDR mode
  • Simple 32-bit master interface to DMA data into user memory space
  • Selectable maximum block size from 512 to 16Kbytes.
  • Supports CPRM security commands and rev 3.0 extended command set

Device Utilization and Performance

3300 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

IP Quality Metrics

Basic
Year IP was first released2004
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportOS independent
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Verification
Simulators supportedVerilog/VHDL
Hardware validated Y. Altera Board Name Custom build board
Industry standard compliance testing performed
Y
If yes, which test(s)?SD Specification
If yes, on which Altera device(s)?Cyclone
If Yes, date performed
01/01/2004
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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