Synchronous ONFI NAND Flash Controller (EP502)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V


The EP502 NAND Flash controller provides a simple interface for user to access SLC and MLC NAND Flash devices. The EP502 manages all the hardware protocols and allows the user to access NAND Flash memory simply by reading and writing control registers of the IP core. The EP502 supports both synchronous and asynchronous double data rate data transfer and is ONFI compliant. It provides much higher data throughput than traditional asynchronous NAND interface. Hardware generated ECC provides the required multi-bit ECC protection for NAND Flash devices. BCH code is used for multi-bit ECC up to 60 bits per 512 or 1k byte data block. Error correction can be done in hardware or software to allow different optimization between size and performance. The EP502 offers many features to improve system performance including DMA, boot ROM support, and a wide choice of user interfaces such as AHB, AXI, Avalon, PLB, wishbone and generic bus.


    Device Utilization and Performance

    2000 LE, 150 MHz

    Getting Started

    For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: WWW:

    IP Quality Metrics

    Year IP was first released2004
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportOS independent
    User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
    IP-XACT Metadata includedN
    Simulators supportedVerilog/VHDL
    Hardware validated Y. Altera Board Name Custom build board
    Industry standard compliance testing performed
    If yes, which test(s)?ONFI
    If yes, on which Altera device(s)?Cyclone
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  Y

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