MIPI-CSI2 Transmit Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Overview

The Foresys MIPI Core provides a fast path to integrating Image Sensors into a wide variety of products based on Altera devices. It is designed to convert an internal payload agnostic Avalon Streaming data bus to MIPI/CSI2 data

Features

  • Provides compatible MIPI D-Phy v1.1 physical layer using FPGA LVDS/LVCMOS IO and passive network

Device Utilization and Performance

950 LEs, 3 M9Ks and 1 PLL for a 1 data lane version

Getting Started

Email ip@foresy.com for an evaluation package

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNA
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim-AE
Hardware validated Y. Altera Board Name Max10 IO dev Kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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