Graphics Accelerator for Android

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Test & Measurement

Evaluation Method: Source Code

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Arria V SoC

Cyclone Series: Cyclone V SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

FUJISOFT developed a Graphics Accelerator IP core that can boost graphical processing when using an Altera SoC device. We implemented a smooth-running Android OS onto Altera SoC to demonstrate the IP's performance capabilities. FUJISOFT created an Android platform that includes the standard open source Android OS verion 4.0.4 ICS running on top of the Linux Kernal from Altera's BSP. Android graphics processing is supported in the FPGA using the FUJISOFT IP core.

Features

  • Low price
  • Includes Driver and Android HAL
  • Accelerates the Android drawing process
  • Small size

Device Utilization and Performance

Cyclone? V SoC Development Kit (Altera) Multi-touch LCD Module?Terasic? Resolution 800x480 Pixels with GRAPHICS ACCELERATOR for Android\tvs. without GRAPHICS ACCELERATOR for Android 1. CPU usage???\t19.0 (with)\t48.8 (without) 2.Frame rate?fps]\t55 (with)\t33 (without)

Getting Started

Android has grown to be the number one smartphone operating system. While Android continues to be the most popular OS for smartphones and tablets, it is also being adopted for other embedded devices and industrial equipment. However, high-performance CPUs are rarely used in embedded applications and the implementation of relatively low-performing CPUs will slow down the Android drawing process. This product is the solution!

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Non
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNIOS II
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedNo
Hardware validated Y. Altera Board Name Cyclone? V SoC Development Kit (Altera)
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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