PCIE Standard Fpga GPIO Card with EP4CGX15/EP4CGX30 Fpga

Board Image

Block Diagram

Board Category: Production Ready Board, Development Kit

Components & Interface: Expansion: Santa Cruz; Industry Standard: PCIE Edge

End Market: Computer & Storage, Industrial, Medical, Test & Measurement

Technology: Embedded Design, Interface Protocols

Board Feature: General User IO: LED

Cyclone Series: Cyclone IV: Cyclone IV GX

Overview

GEB PCIe Fpga card is the flexible solution to interface many equipments to a PC. The make it easy, a two pieces solution has been applied, splitting the interface on two boards. The PCie Fpga Card, appropriately programmed, will host the protocols of interface, standard or custom, serial or parallel, RZ, NRZ, Manchester, HDLC…. everything you would like to have. A second one will be daughter board, a simple electrical interface board. It will host the glue logic needed to meet the interfaced system specification, RS232, RS422, RS485, LVDS, +28V discrete, opto coupled, and so on

Order Information

Ordering Code
Pricing
Buy
100815A1$292Buy Now

Development Kit Hardware Contents

  • 100815A1 Card Equipped with EP4CGX15BF14C7N Fpga, Santa Cruz header terminals

Development Kit Software Contents

  • -Executable Demo program (Pio Read and Write) under Linux and Windows
  • -Fpga Configuration File with 7xPIO

Support Document

File Name
Description
Version
doc-us-dsnbk-112-3402001201418-171122um-rev-a-mb-psoc-m10.pdfPCIe-15-IO USER’S MANUAL0.0

Board Quality Metrics

Basic
Latest version of Quartus supported 17.0
Required Collateral Available
User Guide Y
Board Schematics N
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

N/A
Parts per Million (PPM)
N/A
Board Policy
Return Material Authorization (RMA) Policy Units older than 10 years are considered no more repairable. Units under warranty are repaired without charges unless hardware fault is due to manumission or external causes.
Compliance
RoHS Compliant Y
CE Compliant Y. 2011/65/ec
Conflict Mineral Policy Compliant
Y
Test Plan Summary

Boundary Scan Test of all interconnections, including PCIE lanes. Dynamic Functional Tests with PIO FPGA system on Intel Moherboards

Additional Compliance
ISO 9000 & 9001

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.