The ProceV system is based on Altera's newest generation Stratix V FPGA device. The ProceV provides massive capacity (up to 952K LEs), and high memory and I/O performance. In addition to 8-Lane PCIe gen 3, twenty six 12.5 Gb/s transceivers provide external IOs of up to 260 Gb/s (full duplex). The combination of high-speed direct communication to the FPGA via PCIe, CXP, SFP+, and General Purpose high-speed transceivers makes the ProceV ideal for low-latency, high performance networking and HPC applications. Powerful memory scheme, composed of embedded memory with 8 TB/s throughput, 16 GB ECC DDR III and optional 288 Mb DDR II SRAM, enables high bandwidth computation and networking, and unique flexibility to achieve diverse algorithm architectures. Using a Gidel or user dedicated add-on daughter boards, the FPGA device can directly interface with standard protocols such as CoaXPress, HDMI, SDI and Camera Link as well as additional interface options including QSFP and SAS/SATA. Eight-lane PCIe Gen. 3 interface allows for strong co-processing between a standard PC operating system and an FPGA based accelerator.
- 8-lane PCI Express Gen3 (PCIe x8) for up to 10 GB/s sustain throughput
- 1 CXP connector cage suitable for 100 Gigabit Ethernet (100GBASE-CR10, 100GBASE-SR10), 3×40 Gigabit Ethernet, or single Infiniband 12×QDR link
- 2 SFP+ cage suitable for 10 Gigabit Ethernet and Optical Transport Network
- Up to 16 GB of DDR3 at up to 19.2 GB/s sustain access
- Optional: up to 2×144Mb SRAM memories (up to 450Mhz) at a sustain throughput of 6.4 GB/s
- Gidel ProcWizard: Powerful software for developing and debugging of HDL design and Software driver
- OpenCL SDK: The Gidel OpenCL bundle based on Altera's SDK provides means to develop on the Gidel acceleration boards using C-base syntax language.
- Quartus II software : Altera's tools kit enabling Gidel's users to develop, debug and compile HDL code
- C/C++ API in Windows and Linux OS
- ProcMultiPort DRAM controller: Gidel's unique IPs enable customized multiple parallel data streaming to feed computational processing
Board Quality Metrics
|Latest version of Quartus supported||15.1|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)||N/A|
|Return Material Authorization (RMA) Policy||Contact Gidel|
|CE Compliant||N. It is not for boards-only for systems|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
Gidel's Proc Development Kit is a set of building blocks designed to facilitate the development task and the hardware-software integration, and to enhance significantly system productivity. It is a complete system solution including boards, software tools, IPs and optional daughter boards. \nIn addition Gidel provides a GUI based diagnostics tool(ProcDiagnostics) to test the components of the PCIe based FPGA platform.
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