HyperLink High Speed DSP Interface Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V

Cyclone Series: Cyclone V

Stratix Series: Stratix V

Overview

The Integretek HyperLink FPGA core leverages the proven TI HyperLink technology connecting your FPGA design to a Texas Instruments C66X multi-core DSP at link rates up to 25 Gb/s. The Integretek HyperLink Core allows the creation of a user defined system which can communicate with remote TI Cx66 DSP devices via a high speed SERDES interface. Developers can choose either an industry standard AXI4 bus or DMA interface. The HyperLink IP is available in both a x4 lane configuration and low cost x1 lane configuration.

Features

    Device Utilization and Performance

    The HyperLink protocol supports data rates up to 25Gbps. Actual data rates will depend on available transceiver speed and hardware implementation. Available HyperLink data rates in Gbps are as follows (lane/x4): 1.25/5 Gbps 3.125/12 Gbps 6.25/25 Gbps 10/40 Gbps (pending)

    Getting Started

    Refer to the HyperLink High Speed DSP Interface FPGA Core User Manual for integration details.

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceAXI; Other: DMA Master/Slave
    IP-XACT Metadata includedN
    Verification
    Simulators supportedMentor Questa
    Hardware validated Y. Altera Board Name Arria 10 GX Dev Kit DK-DEV-10AX115S-A
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.